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DC poleHodnotaJazyk
dc.contributor.authorBrychcín, Jiří
dc.contributor.authorKošan, Tomáš
dc.contributor.authorPeroutka, Zdeněk
dc.contributor.editorPinker, Jiří
dc.date.accessioned2021-10-27T08:47:40Z
dc.date.available2021-10-27T08:47:40Z
dc.date.issued2021
dc.identifier.citation2021 International Conference on Applied Electronics: Pilsen, 7th – 8th September 2021, Czech Republic, p. 21-24.en
dc.identifier.isbn978–80–261–0972–3 (Print)
dc.identifier.isbn978–80–261–0973–0 (Online)
dc.identifier.issn1803–7232 (Print)
dc.identifier.issn1805–9597 (Online)
dc.identifier.urihttp://hdl.handle.net/11025/45558
dc.description.sponsorshipStudent Grant System SGS-2021-021en
dc.format4 s.cs
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.publisherUniversity of West Bohemiaen
dc.rights© University of West Bohemia, 2021en
dc.subjectmodulátorcs
dc.subjectvyvažovánícs
dc.subjectmodelcs
dc.subjectsimulacecs
dc.subjectimplementacecs
dc.subjectvíceúrovňovécs
dc.subjectkondenzátorycs
dc.titleUniversal balancing method of flying capacitor convertersen
dc.typeconferenceObjecten
dc.typekonferenční příspěvekcs
dc.rights.accessopenAccessen
dc.type.versionpublishedVersionen
dc.description.abstract-translatedThis paper describes novel method of balancing of multi-level flying capacitor converters. The proposed balancing block is placed behind PWM modulator instead of balancing table and it is independent on type of modulator nor number of levels. The method was simulated in ModelSIM and PLECS/Simulink and implemented in VHDL to FPGA. Function of the proposed algorithm was verified on the real seven level flying capacitor converter with three phase asynchronous machine.en
dc.subject.translatedmodulatoren
dc.subject.translatedbalancingen
dc.subject.translatedmodelen
dc.subject.translatedsimulationen
dc.subject.translatedimplementationen
dc.subject.translatedmultilevelen
dc.subject.translatedflyingen
dc.subject.translatedcapacitorsen
dc.type.statusPeer-revieweden
Vyskytuje se v kolekcích:Applied Electronics 2021

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